diff --git a/arch/x86/include/asm/arch-coreboot/gpio.h b/arch/x86/include/asm/arch-coreboot/gpio.h
index 3ec1816..4951a8c 100644
--- a/arch/x86/include/asm/arch-coreboot/gpio.h
+++ b/arch/x86/include/asm/arch-coreboot/gpio.h
@@ -7,9 +7,4 @@
 #ifndef _X86_ARCH_GPIO_H_
 #define _X86_ARCH_GPIO_H_
 
-struct ich6_bank_platdata {
-	uint32_t base_addr;
-	const char *bank_name;
-};
-
 #endif /* _X86_ARCH_GPIO_H_ */
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index 290a737..ae338e3 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -142,6 +142,22 @@
 #define FD2		0x3428	/* 32bit */
 #define CG		0x341c	/* 32bit */
 
+/* ICH7 GPIOBASE */
+#define GPIO_USE_SEL	0x00
+#define GP_IO_SEL	0x04
+#define GP_LVL		0x0c
+#define GPO_BLINK	0x18
+#define GPI_INV		0x2c
+#define GPIO_USE_SEL2	0x30
+#define GP_IO_SEL2	0x34
+#define GP_LVL2		0x38
+#define GPIO_USE_SEL3	0x40
+#define GP_IO_SEL3	0x44
+#define GP_LVL3		0x48
+#define GP_RST_SEL1	0x60
+#define GP_RST_SEL2	0x64
+#define GP_RST_SEL3	0x68
+
 /* ICH7 PMBASE */
 #define PM1_STS		0x00
 #define   WAK_STS	(1 << 15)
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index ff9574c..4ea46d7 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -33,6 +33,7 @@
 	uint32_t bist;			/* Built-in self test value */
 	struct pci_controller *hose;	/* PCI hose for early use */
 	enum pei_boot_mode_t pei_boot_mode;
+	const struct pch_gpio_map *gpio_map;	/* board GPIO map */
 };
 
 #endif
diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h
index 8bda414..5540d42 100644
--- a/arch/x86/include/asm/gpio.h
+++ b/arch/x86/include/asm/gpio.h
@@ -1,12 +1,152 @@
 /*
  * Copyright (c) 2012, Google Inc. All rights reserved.
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0
  */
 
 #ifndef _X86_GPIO_H_
 #define _X86_GPIO_H_
 
+#include <linux/compiler.h>
 #include <asm/arch/gpio.h>
 #include <asm-generic/gpio.h>
 
+struct ich6_bank_platdata {
+	uint32_t base_addr;
+	const char *bank_name;
+};
+
+#define GPIO_MODE_NATIVE	0
+#define GPIO_MODE_GPIO		1
+#define GPIO_MODE_NONE		1
+
+#define GPIO_DIR_OUTPUT		0
+#define GPIO_DIR_INPUT		1
+
+#define GPIO_NO_INVERT		0
+#define GPIO_INVERT		1
+
+#define GPIO_LEVEL_LOW		0
+#define GPIO_LEVEL_HIGH		1
+
+#define GPIO_NO_BLINK		0
+#define GPIO_BLINK		1
+
+#define GPIO_RESET_PWROK	0
+#define GPIO_RESET_RSMRST	1
+
+struct pch_gpio_set1 {
+	u32 gpio0:1;
+	u32 gpio1:1;
+	u32 gpio2:1;
+	u32 gpio3:1;
+	u32 gpio4:1;
+	u32 gpio5:1;
+	u32 gpio6:1;
+	u32 gpio7:1;
+	u32 gpio8:1;
+	u32 gpio9:1;
+	u32 gpio10:1;
+	u32 gpio11:1;
+	u32 gpio12:1;
+	u32 gpio13:1;
+	u32 gpio14:1;
+	u32 gpio15:1;
+	u32 gpio16:1;
+	u32 gpio17:1;
+	u32 gpio18:1;
+	u32 gpio19:1;
+	u32 gpio20:1;
+	u32 gpio21:1;
+	u32 gpio22:1;
+	u32 gpio23:1;
+	u32 gpio24:1;
+	u32 gpio25:1;
+	u32 gpio26:1;
+	u32 gpio27:1;
+	u32 gpio28:1;
+	u32 gpio29:1;
+	u32 gpio30:1;
+	u32 gpio31:1;
+} __packed;
+
+struct pch_gpio_set2 {
+	u32 gpio32:1;
+	u32 gpio33:1;
+	u32 gpio34:1;
+	u32 gpio35:1;
+	u32 gpio36:1;
+	u32 gpio37:1;
+	u32 gpio38:1;
+	u32 gpio39:1;
+	u32 gpio40:1;
+	u32 gpio41:1;
+	u32 gpio42:1;
+	u32 gpio43:1;
+	u32 gpio44:1;
+	u32 gpio45:1;
+	u32 gpio46:1;
+	u32 gpio47:1;
+	u32 gpio48:1;
+	u32 gpio49:1;
+	u32 gpio50:1;
+	u32 gpio51:1;
+	u32 gpio52:1;
+	u32 gpio53:1;
+	u32 gpio54:1;
+	u32 gpio55:1;
+	u32 gpio56:1;
+	u32 gpio57:1;
+	u32 gpio58:1;
+	u32 gpio59:1;
+	u32 gpio60:1;
+	u32 gpio61:1;
+	u32 gpio62:1;
+	u32 gpio63:1;
+} __packed;
+
+struct pch_gpio_set3 {
+	u32 gpio64:1;
+	u32 gpio65:1;
+	u32 gpio66:1;
+	u32 gpio67:1;
+	u32 gpio68:1;
+	u32 gpio69:1;
+	u32 gpio70:1;
+	u32 gpio71:1;
+	u32 gpio72:1;
+	u32 gpio73:1;
+	u32 gpio74:1;
+	u32 gpio75:1;
+} __packed;
+
+/*
+ * This hilariously complex structure came from Coreboot. The
+ * setup_pch_gpios() function uses it. It could be move to device tree, or
+ * adjust to use masks instead of bitfields.
+ */
+struct pch_gpio_map {
+	struct {
+		const struct pch_gpio_set1 *mode;
+		const struct pch_gpio_set1 *direction;
+		const struct pch_gpio_set1 *level;
+		const struct pch_gpio_set1 *reset;
+		const struct pch_gpio_set1 *invert;
+		const struct pch_gpio_set1 *blink;
+	} set1;
+	struct {
+		const struct pch_gpio_set2 *mode;
+		const struct pch_gpio_set2 *direction;
+		const struct pch_gpio_set2 *level;
+		const struct pch_gpio_set2 *reset;
+	} set2;
+	struct {
+		const struct pch_gpio_set3 *mode;
+		const struct pch_gpio_set3 *direction;
+		const struct pch_gpio_set3 *level;
+		const struct pch_gpio_set3 *reset;
+	} set3;
+};
+
+void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
+
 #endif /* _X86_GPIO_H_ */
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index d3381b0..b095d17 100644
--- a/drivers/gpio/intel_ich6_gpio.c
+++ b/drivers/gpio/intel_ich6_gpio.c
@@ -33,6 +33,11 @@
 #include <pci.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
+#include <asm/pci.h>
+#ifdef CONFIG_X86_RESET_VECTOR
+#include <asm/arch/pch.h>
+#define SUPPORT_GPIO_SETUP
+#endif
 
 #define GPIO_PER_BANK	32
 
@@ -46,6 +51,53 @@
 	uint32_t lvl;
 };
 
+#ifdef SUPPORT_GPIO_SETUP
+static void setup_pch_gpios(const struct pch_gpio_map *gpio)
+{
+	u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
+
+	/* GPIO Set 1 */
+	if (gpio->set1.level)
+		outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
+	if (gpio->set1.mode)
+		outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
+	if (gpio->set1.direction)
+		outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
+	if (gpio->set1.reset)
+		outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
+	if (gpio->set1.invert)
+		outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
+	if (gpio->set1.blink)
+		outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
+
+	/* GPIO Set 2 */
+	if (gpio->set2.level)
+		outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
+	if (gpio->set2.mode)
+		outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
+	if (gpio->set2.direction)
+		outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
+	if (gpio->set2.reset)
+		outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
+
+	/* GPIO Set 3 */
+	if (gpio->set3.level)
+		outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
+	if (gpio->set3.mode)
+		outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
+	if (gpio->set3.direction)
+		outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
+	if (gpio->set3.reset)
+		outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
+}
+
+/* TODO: Move this to device tree, or platform data */
+void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
+{
+	gd->arch.gpio_map = map;
+}
+#endif /* SUPPORT_GPIO_SETUP */
+
 static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
 {
 	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
@@ -60,13 +112,13 @@
 	pci_dev = PCI_BDF(0, 0x1f, 0);
 
 	/* Is the device present? */
-	pci_read_config_word(pci_dev, PCI_VENDOR_ID, &tmpword);
+	tmpword = pci_read_config16(pci_dev, PCI_VENDOR_ID);
 	if (tmpword != PCI_VENDOR_ID_INTEL) {
 		debug("%s: wrong VendorID\n", __func__);
 		return -ENODEV;
 	}
 
-	pci_read_config_word(pci_dev, PCI_DEVICE_ID, &tmpword);
+	tmpword = pci_read_config16(pci_dev, PCI_DEVICE_ID);
 	debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword);
 	/*
 	 * We'd like to validate the Device ID too, but pretty much any
@@ -76,34 +128,34 @@
 	 */
 
 	/* I/O should already be enabled (it's a RO bit). */
-	pci_read_config_word(pci_dev, PCI_COMMAND, &tmpword);
+	tmpword = pci_read_config16(pci_dev, PCI_COMMAND);
 	if (!(tmpword & PCI_COMMAND_IO)) {
 		debug("%s: device IO not enabled\n", __func__);
 		return -ENODEV;
 	}
 
 	/* Header Type must be normal (bits 6-0 only; see spec.) */
-	pci_read_config_byte(pci_dev, PCI_HEADER_TYPE, &tmpbyte);
+	tmpbyte = pci_read_config8(pci_dev, PCI_HEADER_TYPE);
 	if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) {
 		debug("%s: invalid Header type\n", __func__);
 		return -ENODEV;
 	}
 
 	/* Base Class must be a bridge device */
-	pci_read_config_byte(pci_dev, PCI_CLASS_CODE, &tmpbyte);
+	tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_CODE);
 	if (tmpbyte != PCI_CLASS_CODE_BRIDGE) {
 		debug("%s: invalid class\n", __func__);
 		return -ENODEV;
 	}
 	/* Sub Class must be ISA */
-	pci_read_config_byte(pci_dev, PCI_CLASS_SUB_CODE, &tmpbyte);
+	tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE);
 	if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) {
 		debug("%s: invalid subclass\n", __func__);
 		return -ENODEV;
 	}
 
 	/* Programming Interface must be 0x00 (no others exist) */
-	pci_read_config_byte(pci_dev, PCI_CLASS_PROG, &tmpbyte);
+	tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_PROG);
 	if (tmpbyte != 0x00) {
 		debug("%s: invalid interface type\n", __func__);
 		return -ENODEV;
@@ -114,7 +166,7 @@
 	 * that it was unused (or undocumented). Check that it looks
 	 * okay: not all ones or zeros, and mapped to I/O space (bit 0).
 	 */
-	pci_read_config_dword(pci_dev, PCI_CFG_GPIOBASE, &tmplong);
+	tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
 	if (tmplong == 0x00000000 || tmplong == 0xffffffff ||
 	    !(tmplong & 0x00000001)) {
 		debug("%s: unexpected GPIOBASE value\n", __func__);
@@ -140,12 +192,18 @@
 	return 0;
 }
 
-int ich6_gpio_probe(struct udevice *dev)
+static int ich6_gpio_probe(struct udevice *dev)
 {
 	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
 	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
 	struct ich6_bank_priv *bank = dev_get_priv(dev);
 
+#ifdef SUPPORT_GPIO_SETUP
+	if (gd->arch.gpio_map) {
+		setup_pch_gpios(gd->arch.gpio_map);
+		gd->arch.gpio_map = NULL;
+	}
+#endif
 	uc_priv->gpio_count = GPIO_PER_BANK;
 	uc_priv->bank_name = plat->bank_name;
 	bank->use_sel = plat->base_addr;
@@ -155,7 +213,8 @@
 	return 0;
 }
 
-int ich6_gpio_request(struct udevice *dev, unsigned offset, const char *label)
+static int ich6_gpio_request(struct udevice *dev, unsigned offset,
+			     const char *label)
 {
 	struct ich6_bank_priv *bank = dev_get_priv(dev);
 	u32 tmplong;